# Sequential Logic Circuits MCQs

## A _________ shift register can shift stored data either left or right.

• A. bidirectional
• B. tri-state
• C. universal
• D. bidirectional universal

## A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.

• A. right, one
• B. right, two
• C. left, one
• D. left, three

## A comparison between ring and johnson counters indicates that:

• A. a ring counter has fewer flip-flops but requires more decoding circuitry
• B. a ring counter has an inverted feedback path
• C. a johnson counter has more flip-flops but less decoding circuitry
• D. a johnson counter has an inverted feedback path

## A ripple counter’s speed is limited by the propagation delay of:

• A. each flip-flop
• B. all flip-flops and gates
• C. the flip-flops only with gates
• D. only circuit gates

## A sequence of equally spaced timing pulses may be easily generated by a(n) __________.

• A. ring counter
• B. johnson counter
• C. binary up counter
• D. ripple counter

## A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

• A. shift register sequencer
• B. clock
• C. johnson
• D. binary

• A. toggle
• B. ripple
• C. binary
• D. flip-flop

## In order to use a shift register as a counter, ________.

• A. the register's serial input is the counter input and the serial output is the counter output
• B. the parallel inputs provide the input signal and the output signal is taken from the serial data output
• C. a serial-in, serial-out register must be used
• D. the serial output of the register is connected back to the serial input of the register

## Mod-6 and mod-12 counters are most commonly used in:

• A. frequency counters
• B. multiplexed displays
• C. digital clocks
• D. power consumption meters

## One of the major drawbacks to the use of asynchronous counters is that:

• A. low-frequency applications are limited because of internal propagation delays
• B. high-frequency applications are limited because of internal propagation delays
• C. Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.
• D. Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications.

## Ring and johnson counters are _______.

• A. asynchronous counters
• B. synchronous counters
• C. true binary counters
• D. asynchronous and true binary counters

## Synchronous construction reduces the delay time of a counter to the delay of __________.

• A. all flip-flops and gates
• B. a single flip-flop and a gate
• C. all flip-flops and gates after a 3 count
• D. a single gate

## Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

• A. input clock pulses are applied only to the first and last stages
• B. input clock pulses are applied only to the last stage
• C. input clock pulses are not used to activate any of the counter stages
• D. input clock pulses are applied simultaneously to each stage

• B. strobing
• C. ring
• D. BCD

## To operate correctly, starting a ring counter requires __________.

• A. clearing one flip-flop and presetting all the others
• B. clearing all the flip-flops
• C. presetting one flip-flop and clearing all the others
• D. presetting all the flip-flops

## To operate correctly, starting a ring counter requires:

• A. clearing all the flip-flops
• B. presetting one flip-flop and clearing all the others
• C. clearing one flip-flop and presetting all the others
• D. presetting all the flip-flops

## What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?

• A. The output word decreases by 1.
• B. The output word decreases by 2.
• C. The output word increases by 1.
• D. The output word increases by 2.

## What is a shift register that will accept a parallel input and can shift data left or right called?

• A. tri-state
• B. end around
• C. bidirectional universal
• D. conversion

• A. Shifting the data in all flip-flops simultaneously
• C. Loading data in all four flip-flops at the same time
• D. Momentarily disabling the synchronous SET and RESET inputs

• A. PIPO
• B. SISO
• C. SIPO
• D. PISO

## When the output of a tri-state shift register is disabled, the output level is placed in a:

• A. float state
• B. LOW state
• C. high impedance state
• D. float state and a high impedance state

## When two counters are cascaded, the overall mod number is equal to the __________ of their individual mod numbers.

• A. product
• B. sum
• C. log
• D. reciprocal