Flip-Flops And Timers MCQs

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A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?

  • A. AND or OR gates
  • B. XOR or XNOR gates
  • C. NOR or NAND gates
  • D. AND or NOR gates
  • Correct Answer: Option C

A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be _________ ms.

  • A. 3
  • B. 7
  • C. 10
  • D. 13
  • Correct Answer: Option D

An astable multivibrator is a circuit that:

  • A. has two stable states
  • B. is free-running
  • C. produces a continuous output signal
  • D. is free-running and produces a continuous output signal
  • Correct Answer: Option C

An S-R flip-flop can be triggered by ______, ______, or ________.

  • B. edges, levels, pulses
  • C. HIGHs, LOWs, CLEARs
  • D. SETs, RESETs, HIGHs
  • Correct Answer: Option B

An S-R NAND latch with both of its inputs LOW has an output that is _____________.

  • A. unpredictable
  • B. floating
  • C. HIGH
  • D. LOW
  • Correct Answer: Option A

Edge-triggered flip-flops must have _________.

  • A. very fast response times
  • B. at least two inputs to handle rising and falling edges
  • C. a positive-transition pulse generator
  • D. a negative-transition pulse generator
  • Correct Answer: Option C

For an S-R flip-flop to be SET or RESET, the respective input must be __________.

  • A. LOW
  • B. HIGH
  • C. installed with steering diodes
  • D. in parallel with a limiting resistor
  • Correct Answer: Option B

If an input is activated by a signal transition, it is _____________.

  • A. edge-triggered
  • B. toggle-triggered
  • C. clock-triggered
  • D. noise-triggered
  • Correct Answer: Option A

If both inputs of an S-R NAND latch are LOW, what will happen to the output?

  • A. The output would become unpredictable.
  • B. The output will toggle.
  • C. The output will reset.
  • D. No change will occur in the output.
  • Correct Answer: Option A

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

  • A. asynchronous operation
  • B. low input voltages
  • C. gate impedance
  • D. cross coupling
  • Correct Answer: Option D

One example of the use of an S-R flip-flop is as a(n) _________.

  • A. racer
  • B. binary storage register
  • C. astable oscillator
  • D. transition pulse generator
  • Correct Answer: Option B

One example of the use of an S-R flip-flop is as a(n):

  • A. transition pulse generator
  • B. astable oscillator
  • C. racer
  • D. switch debouncer
  • Correct Answer: Option D

Pulse-triggered flip-flops are also called _________ flip-flops.

  • A. master-slave
  • B. postponed
  • C. level
  • D. edge
  • Correct Answer: Option A

The 555 timer can be used in which of the following configurations?

  • A. astable, monostable
  • B. monostable, bistable
  • C. astable, toggled
  • D. bistable, tristable
  • Correct Answer: Option A

The S-R, D-type, and J-K flip-flops are all examples of _________________.

  • A. astable multivibrators
  • B. bistable multivibrators
  • C. monostable multivibrators
  • D. tristable multivibrators
  • Correct Answer: Option B

The truth table for an S-R flip-flop has how many VALID entries?

  • A. 3
  • B. 1
  • C. 4
  • D. 2
  • Correct Answer: Option A

What is another name for a one-shot?

  • A. monostable
  • B. bistable
  • C. astable
  • D. tristable
  • Correct Answer: Option A

What is one disadvantage of an S-R flip-flop?

  • A. It has no Enable input.
  • B. It has a RACE condition.
  • C. It has no clock input.
  • D. It has only a single output.
  • Correct Answer: Option B

What is the significance of the J and K terminals on the J-K flip-flop?

  • A. There is no known significance in their designations.
  • B. The J represents "jump," which is how the Q output reacts whenever the clock goes HIGH and the J input is also HIGH.
  • C. The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop.
  • D. All of the other letters of the alphabet are already in use.
  • Correct Answer: Option A

When both inputs of a J-K flip-flop cycle, the output will:

  • A. be invalid
  • B. not change
  • C. change
  • D. toggle
  • Correct Answer: Option B

Which of the following describes the operation of a positive edge-triggered D-type flip-flop?

  • A. If both inputs are HIGH, the output will toggle.
  • B. The output will follow the input on the leading edge of the clock.
  • C. When both inputs are LOW, an invalid state exists.
  • D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
  • Correct Answer: Option B

Which of the following is correct for a gated D-type flip-flop?

  • A. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
  • B. The output complement follows the input when enabled.
  • C. Only one of the inputs can be HIGH at a time.
  • D. The output toggles if one of the inputs is held HIGH.
  • Correct Answer: Option A